Level-shifting amplifiers include a class of amplifiers which shifts an input signal by a predetermined voltage. In some situations, it is desirable to handle an input signal with a range that extends beyond a supply voltage (i.e. rail) of a circuit. As set forth below, various circuits exist for such level-shifting purposes.
Prior art FIG. 1 illustrates an exemplary level-shifting amplifier circuit 100, in accordance with the prior art. Such circuit 100 includes an inverting operational amplifier LM324 with a non-inverting input coupled to ground. In use, the circuit 100 serves as a single-supply device powered by a positive rail with a return to ground. Since an input signal is inverted at an output signal of the circuit 100, the input signal may range from ground down to a negative voltage. Further, the output signal may swing from ground up to some (other) positive voltage determined by a ratio of feedback resistors R1, R2. Of course, the input impedance of the circuit 100 is the value of the input resistor R1.
Prior art FIG. 2 illustrates another exemplary level-shifting amplifier circuit 200, in accordance with the prior art. As shown, the instant circuit 200 dangles an emitter and base of a first pair of NPN bipolar transistors Q1, Q2 from a positive rail. Since all junction-isolated nodes are biased near the positive rail, an input signal may range as high as the positive rail minus a couple of volts down below a negative rail (ground) until a break down occurs. Depending on the design of the circuit 200, either the first transistor pair Q1, Q2 or a second transistor pair Q3, Q4 will break down first. The present circuit 200 is typically used in instrumentation amplifiers and high-speed digital line receivers. Further, the input signal being sensed generally must provide bias current for an input stage of the circuit 200.
Prior art FIG. 3 illustrates yet another exemplary level-shifting amplifier circuit 300, in accordance with the prior art. Such circuit 300 may traditionally be found in adjustable voltage regulators. As shown, a bandgap reference voltage Adj dangles below a substrate, which is connected to an output Vout of the circuit 300. A user-supplied resistor divider 302 is provided from the output Vout to a bottom of the reference to ground. The regulated output Vout is set as a function of a ratio of the resistors of the divider 302 times a value of the bandgap reference voltage Adj. Generally, an impedance of the resistive divider 302 is chosen to be fairly low, thus a current of the resistor divider 302 typically swamps a 10-20 uA current from a bottom of the bandgap reference voltage Adj.
Prior art FIGS. 4A and 4B illustrates still yet another exemplary level-shifting amplifier circuit 400, in accordance with the prior art. Such circuit 400 receives an input current i_ref 401 from a bias current generator. The current passes through an n-channel FET NE3 which serves as a power down disconnect. The current also passes through a conventional P-channel cascode current mirror formed by P-channel FETs pe3, pe5, pe6, pe1, pm7 and pm0. It may be noted that the FETs pe5 and pm0 have the same W/L parameters (i.e. width/length dimensions for FET gate, etc.), but the m-numbers (i.e. number of FETs connected in parallel, etc.) are in the ratio of 4:1. Consequently, the current in the output section of the current mirror (source-drain of pm0) is four times that of the input current i_refp.
Still referring to FIGS. 4A and 4B, current mirror output current (that is controlled primarily by FET pm0 and its cascode pm7) passes through a resistive load 421-424. In use, current passes through a source follower formed by a P-channel FET pf2 and an associated cascode device pif2. A voltage at node vout_p 460 is the sum of the input voltage vin_p (at node 470) plus offsets due to the resistive load 421-424 in addition to an offset due to the threshold of the source follower FET 451, and possibly other sources. As shown, gates of the FETs 451, 452 are tied together; this is operable because pif2 is a low threshold voltage type so that a constant 1.1V total appears across the source follower FET 451, thereby greatly increasing the linearity of the level-shifter across its full signal range.
With continued reference to FIGS. 4A and 4B, it should be appreciated that since a current through the resistive load 421-424 may need to generate a potential difference in the hundred(s) of millivolts, a bandwidth of the circuit 400 may become limited. Such an effect would be due to the time constant effect of the resistive load 421-424 working against the capacitance of the FETs 451, 452. In order to overcome excessive bandwidth limitation, an effectively high source impedance current source may formed by FET pair pe18 and pe19 to improve slew rate. This current source may be mirrored by a mirror circuit 485 from a supplied bias current ib using FETs pe30, pe22, pe23, pe24, pe25 working into FET pe18 and cascode FET pe19. It should also be appreciated that the action of the shifter in translating vin_p at node 470 to an offset vout_p at node 460 is for half (by convention the positive half) of a pair of differential signals. An entire duplicate shift arm of circuitry 490 exists for the negative signals vin_n to vout_n. That vin_p and vin_n are offset by a voltage which is set in both cases by current i_refp reflects the need for both signals to be offset by a near identical amount in order to avoid introducing error into the differential signal.
In use, the circuit 400 exhibits poor linearity with signals that exceed VTO beyond the rail. More information regarding such circuit 400 may be found with reference to U.S. Pat. No. 6,717,451.
Unfortunately, prior art amplifiers that level-shift a signal beyond a rail exhibit a low input impedance, or other characteristics that may potentially be undesirable. For example, some prior art amplifiers require a source to provide a significant bias current to power an input stage of the amplifier, etc. There is thus a need for overcoming these and/or other problems associated with the prior art.